In partial fulfilment of the graduation reqirement for a bachelors of science in microelectronic engineering, I am conducting my senior research project this quarter.
Gate stack engineering, Molybdenum and Molybdenum-nitride as gate material for gate electrode. My project will include the establishment of a modified metal gate PMOS process for RIT's manufacturing lab as well as investigation of the effects of work function differences in transistor operation.
Reviewed the metal gate PMOS process this week. I'd decided to only do PMOS based on suggestions from advisors based on the fact that it's the only process we have that forms the gate fast. Although Mo could withstand the furnace temperatures that other RIT processes (CMOS) require, everyone seems to agree that metal in the furnace is just a bad idea. I got all but three certifications this week, ordered my wafers, and began simulation of the M-gate PMOS process with SILVACO. I'm seeing there are some issues I'll have to deal with in a week or two.
1. I will have to talk to T.G. about locating a fight lith mask for S/D formation. Although the Al gate process allows for the same metal to contact source and drain, the same is not for Mo gate. The original process forms source & drain with the gate. Dr. H. and Dr. K. have pointed out to me that I want to avoid rectifying contacts to source and drain. Despite having had two device classes I have further understanding to gain.
2. The established RIT metal gate processes Boron-doped spin-on-glass. I've received cursory instruction on the methods of simulation of this technique with SILVACO. This application of the S/D regions is the first point on my process where a split will be made. Some wafers will receive SOG, others will have S/D implats with B11. Check that, I need FOUR certifications...
3. After acquiring a 4" Mo target for sputtering, I need to establish a deposition rate for the gate region. Dr. R. has given me a name of a grad student who can help me with the development of a sputter process.
4. I will need to also establish a Mo etch process in the fab & confirm I only need to modify the Al etch already in place.
This week I gained 2 more certifications and have accepted a suggestion to add one more variable to my project. Although the metal gate PMOS process uses spin on dopant, I will use one wafer to implant boron for my source and drain. This will add an alternative process to the R.I.T. community. I found out on Tuesday that the Molybdenum target must still be ordered (although I requested it three weeks ago). My masks have been located, and I have coated a gate oxide on two wafers to establish a deposition rate for the moly as soon as it arrives. I have also spoken to a few tool technicians and have established that the same etch used for Al can also be used to etch Mo.
1. There appears to be some competition for experiments involving the GCA stepper. Because using this tool will require more training than other tools, I am scheduling time to use it with another certified user to ensure an “expert” is with me.
My moly target arrived on Wednesday this week, but I’ve already focused on level one lithography as the week three goal. Tuesday I grew the patterning oxide and had the tool exposure tool reserved for Thursday with Jay as my “coach” for exposure. Thursday, we attempted exposure for level one but could not get the mask to align with the tool before it was time to go to class. I had to come in Friday morning to ash unexposed resist instead of etching my first level pattern. I plan to reattempt level one on Monday.
This week I got the level 1 exposure I'd been trying. Next was the develop and etch to pattern the source and drain openings. This part of the project was uneventful. Then I had to split my "lot" to allow for two wafers to recieve their S/D implants instead of SOG. I spent an entire day this week looking for a dummy wafer to spin on glass inorder to groove & stain after the drivin. I didn't get as many wafers as requested at the beginning of this quarter and am looking for ways to save my wafers. 1. Next week will be implant, drive-in and moly deposition rate experiment(s).
This week my dummy wafers caught up with the rest of my lot. However the implanter was down so the split was not rejoined. I'm faced with the dilemma of processing the rest of my wafers and "re-" processing the implanted wafers later or holding my original lot until I can implant. The S/D implants are important to further process development for the RIT community, but the focus of my project is really the gate material which seems a long way off. Without other classwork and conflicting tool reservations I could theoretically finish my processing this week. Despite my setbacks I surmise I am half-way through my required processing. I will have to take major steps in week six in order to reserve time in this quarter to test my product.
So what do I say... The implant process did not neccesitate a predep furnace proc. before drivein. So why not just skip that step and move forward with the outlined/established RIT metal gate PMOS process? Because the predep consumes silicon in the open areas, that's why. With out that step, I removed the masking oxide and was left with a nicely implanted but perfectly smooth Si wafer. NO 2ND LEVEL ALIGNMENT POSSIBLE! In the words of my friend Jay and Homer Simpson "Doh!" So I guess I'll use these for my MoN designed experiment. Coming up soon. I need to get some new wafers fast and determine whether my other wafers can afford to wait.
Those replacement wafers I got were mis-labled. Thinking they were bare Si (just out of the box and silvery as they should be) I dunked them in HF, and threw them in the furnace to get an oxide for my implant. UGH! they must be epi wafers 'cuz they've now got ~18000A of oxide on them! My furnace proc should only have grown 2000 and a fellow students wafers in the same run confirm it did. I'm not sure what do do next, but the SOG wafers can't wait any longer. I'll move them forward, this weekend. I have a sinking feeling I'm about to fall behind...
Can't write much this week, very busy. The DOE for determining how much nitride to include in the sputter had startling results. Using sheet resistance as metric, I found that no nitrogen gives on resistivity reading, and 3% cuts it in half. 6,9,12, etc all increase the resistance measurment linearly after that. Dr. Jackson wants me to repeat the experiment to confirm, but what about the time? I'll deal with it later, for now, I know I need to have very little N in the ambient (adhesion also an issue at higher conc.) BTW up to sputtered Al but I broke one of the 4 SOG wafers. I've given up on the implant process in the interest of time... and politics. I'll try to salvage the broken wafer for the Al pattern etch this evening.
Problems with lithography and the conference is next week. Soooo much to do.
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